16:00 - 18:00 Registration
18:00   Welcome Party
08:00 - 09:00 Registration
09:00 - 09:10  Opening Ceremony
09:10 - 10:00 INVITED TALK 1: Testing Challenges for Modern FPGAs
Michel Renovell
LIRMM, Montpellier, France
  SESSION 1: Testbench Generation and Modeling
10:00 - 10:20 Testbench Development in a Distributed Collaborative Environment
P. Penkala, D. Stachanczyk, and A. Pawlak
Silesian University of Technology, Poland
10:20 - 10:40 On SSBDD Model Size & Complexity
A. Jutman
Tallinn Technical University, Estonia
10:40 - 11:00 Coffee break
  SESSION 2: Digital Signal Processing & Analysis
11:00 - 11:20 An Explicit Criterion for Adaptive Periodic Noise Canceller Robustness Applied to Feedback Cancellation
J. Timoney, J.B. Foley, and A.Th. Schwarzbacher
National University of Ireland, Ireland
11:20 - 11:40 High-Level Simulation and Prototyping of Software Components Using SystemC
R. Pasko, L. Rynders, and S. Vernalde
IMEC, Leuven, Belgium
11:40 - 12:00 Design and Performance of an AES-Rijndael ASIC
C. Chitu, and M. Glesner
Darmstadt University of Technology, Germany
12:00 - 12:20 Power Estimation with a Markov Model
P. Comiskey, A. Schwarzbacher, and J.B. Foley
Institute of Art, Design and Technology, Ireland
12:20 - 12:40 Skew Compensation for High Speed bus based data transfer
S. Ananda Natarajan, A. D. Shripadaraj, and A. Arasu
Wipro Technologies, India
13:00 - 14:00 Lunch
  SESSION 3: VLSI Digital Design
14:00 - 14:20 VLSI Implementation of an LPC Formant Extractor
T. D. Smith, A. Th. Schwarzbacher, and J. T. Timoney
Dublin Institute of Technology, Ireland
14:20 - 14:40 Low-Complexity Asynchronous Bit-Serial Standard Basis Multiplier for the Finite Field GF(2m)
J. Butaš, Ch-S. Choy, D. Duracková, and Ch-F. Chan
Slovak University of Technology, Slovakia
14:40 - 15:00 VLSI Design of a Scheduler to Support Quality of Service in IP Networks
F. Costantino, L. Fanucci, A. Renieri, and P. Terreni
National Research Council - IEIIT, Pisa, Italy
15:00 - 15:20 The Open Compiler PCL for Compact Programmable Logic Controller
Z. Rozehnal
Czech Technical University in Prague, Czech Republic
15:20 - 15:40 Coffee break
  SESSION 4: IP Design & Microprocessors
15:40 - 16:00 Configurability Approach to Embedded Microprocessor Design
N. Q. Trung, K. Siekierska, A. Kobus, D. Obrebski,N. Lugowski, A. Kokoszka, and N. Q. Minh
Institute of Electron Technology, Warsaw, Poland
16:00 - 16:20 Low Power Design of MP3 Audio Decoder Silicon IP
J. Wasowski, J. Jablocki, and A. Kowalczyk
Institute of Electron Technology, Warsaw, Poland
16:20 - 16:40 A deep submicrometer embedded SRAM compiler
Z. Wu, Z. Gao, and X. He
Tsinghua University, China
16:40 - 17:00 Coffee break
  SESSION 5: Neural Networks & Industrial Applications
17:00 - 17:20 Library of Elements for Integrate-and-Fire Neural Networks Design
D. Hajtᚠand D. Duracková
Slovak University of Technology, Slovakia
17:20 - 17:40 Algorithmic extensions of the SUNRED program
L. Pohl
Budapest University of Technology and Economics, Hungary
17:40 - 18:00 Capacitive couplings in unipolar IC fabrication technologies
J. Novák and J. Foit
Czech Technical University in Prague, Czech Republic
18:00 - 18:20 Noise Reduction of Pulse Signals by Usage of Lock-in Amp Techniques
V. Ac, T. Hornak, and W. Roye
Trencin University of Alexander Dubcek, Slovakia
19:30 Conference Dinner

09:30 - 10:20  INVITED TALK 2: Re-Generalizing the MOS Transistor, For Improved Analog Design and Extension to Nanotechnology: New Rules for a New Century
Daniel Foty
Gilgamesh Associates, Vermont, USA
  SESSION 6: Analog Circuits: Modeling and Simulation
10:20 - 10:40 Low Frequency Noise Measurement and SPICE Noise Modeling for Analog Design
G. Rappitsch and J. Fellner
Austriamicrosystems AG, Austria
10:40 - 11:00 Modelling and Simulation of Analog Circuit Components at Operational Level
S. Lauckner, and J. Kampe
Technical University of Ilmenau, Germany
11:00 - 11:20 Process Characterisation For Analog Circuit Design
E. Seebacher
Austriamicrosystems AG, Austria
11:20 - 11:40 Coffee break
  SESSION 7: Analog Signal Processing
11:40 - 12:00 Switch Resistance Assignment in R-2R Digital/Analog Converter
V. Kukk and E. Kängsep
Tallinn Technical University, Estonia
12:00 - 12:20 A 10 Gb/s CMOS Phase Detector Using Dual Substrate Technique
Z. Hui and T. Kwasniewski
Carleton University, Ottawa, Canada
12:20 - 12:40 A New Logarithmic Curvature-Corrected CMOS Voltage Reference using Offset Voltage Follower and Asymetric Differential Amplifier Blocks
C. Popa
University Politehnica Bucharest, Romania
12:40 - 13:00 Explaining the Unexpected Performance of a Switched-Current Sigma-Delta Modulator
F. Sandoval-Ibarra and R. Rodríguez-Calderón
CINVESTAV-Guadalajara Unit, Mexico
13:00 - 14:00 Lunch
14:00 - 15:00  POSTER SESSION
Comparison of Time-Frequency Biomedical Signal Representation Methods
A. S. Hassan
Slovak University of Technology, Slovakia
VHDL Fault Injection Techniques in Design Phase
D. Dimitrov, A. Andovova, and M. Hristov
Technical University of Sofia, Bulgaria
Design of Microsystems Using Equivalent Models Between Energy Domains
M. Husák and J. Jakovenko
Czech Technical University in Prague, Czech Republic
Measuring Magnetic Fields at Low Temperature
P.J. García-Ramírez, F. Sandoval-Ibarra, and E.A. Gutiérrez-Domínguez
Universidad Cristóbal Colón, Mexico
CMOS Computational Circuits Using Saturated and Bulk-Driven Weak-Inversion MOS Devices
C. Popa
University Politehnica Bucharest, Romania
A Set of Large Time-Step Integration Formulas
V. Kukk
Tallinn Technical University, Estonia
FPGA-based Implementation of a Data Encryption Algorithm with Testability Structures
M. Balaz, T. Pikula, and P. Trebaticky
Slovak Academy of Sciences, Bratislava, Slovakia
Comparison of Two Recursive Constant Modulus Algorithms
A. Hermanek and P. Regalia
Czech Academy of Sciences, Czech Republic
Techniques For Failure Analysis
N. Atanasova, a. Andovova, D. Dimitrov, and C. Nikolova
Technical University of Sofia, Bulgaria
Yield improving using a static reconfiguration of the analog parts
M. Jáchim
ASICentrum, Prague, Czech Republic
Refractory Period Determination in the Hodgkin-Huxley Model of the Nerve Fibre Membrane
E. Cocherova
Slovak University of Technology, Slovakia
  SESSION 8: RF Design & Optical Communication Systems
15:00 - 15:20 A RF Power Detector
M. Koort, E. Kängsep, and V. Kukk
Tallinn Technical University, Estonia
15:20 - 15:40 Design and Investigation of a Class E RF Power Amplifier IC in 0.35 um CMOS Technology for Mobile Communication Systems
M. Tomaska, R. Vazny, and M. Krnac
Slovak University of Technology, Slovakia
15:40 - 16:00 Fiber Ring Laser with Computer Controlled Wavelength Tunability
I. Glesk, L. Xu, D. Rand, and P. R. Prucnal
Princeton University, USA
16:00 - 16:20 Multiple-Access Interference in Optical CDMA System with Non-Ideal Optical Hard-Limiters
J. Chovan. F. Uherek, and P. Habovcik
Slovak University of Technology, Slovakia
16:20 Closing Address
End of the Conference